1. Field of the Invention
This invention relates generally to an A.C. zero crossover detector and, more particularly, to an A.C. zero crossover detector including means for compensating for phase error at both the positive going and negative going crossovers.
2. Description of the Prior Art
The advantages offered by MOS technology are well known; e.g. higher density, greater yield, etc. Thus, smaller MOS device geometries permit a greater number of devices to be produced per unit area or, stated another way, a single MOS device will occupy less space. This characteristic is extremely important in the design and fabrication of complex digital integrated circuits; for example, single chip microprocessors.
Whereas digital circuitry is generally characterized by its "ON/OFF" or "ONE/ZERO" nature, most measurements in the real world are inherently analog; e.g., temperature, pressure, speed, voltage, etc. Therefore, it is necessary that microprocessors and other digital circuitry communicate or interface with analog circuitry such as amplifiers, buffers, comparators, etc., in order to permit digital processing of the analog signals. The required interfacing may be accomplished by providing analog components which are external to the microprocessor chip. However, such arrangements generally require more current, a larger power supply and commonly present more opportunities for design and manufacturing errors. To avoid these disadvantages, analog circuits such as voltage crossover detectors are being manufactured integrally with the digital circuitry; e.g., on the microprocessor chip itself, and due to the complex nature of microprocessors, the inclusion of analog devices on the same chip requires that the same manufacturing process be employed. Thus, for example, a zero crossover detector included on a MOS microprocessor chip must be fabricated in accordance with MOS processing techniques, and the design of the zero crossover detectors must be tailored to such processing techniques.
It is well known that a resistor/capacitor (RC) circuit will cause an applied A.C. signal to be phase shifted thus producing an error in the detection of the zero crossovers of the A.C. signal. This phase shift can be reduced by increasing the resistance; however, this substantially increases the time necessary to charge the capacitor. To avoid this time loss, a controlled amount of hysteresis has been employed to partially compensate for the resulting phase shift. While this enabled detection of the positive going zero crossover point to within .+-.5 degrees, an offset error of 100mu resulted in the detection of the negative going zero crossover point.
Known zero crossover detection circuits suffer additional disadvantages. First, variations in V.sub.R will cause errors to be introduced into the zero crossover detection process. Second, additional errors will be introduced if the controlled amount of hysteresis does not track variations in the biasing circuit due to minor processing and fabrication variations.